*version 8.0 540325598
u 88
@libraries
@analysis
@targets
@attributes
@translators
a 0 u 13 0 0 0 hln 100 TANGO=PCB
a 0 u 13 0 0 0 hln 100 SCICARDS=PCB
a 0 u 13 0 0 0 hln 100 PROTEL=PCB
a 0 u 13 0 0 0 hln 100 PCBOARDS=PCB
a 0 u 13 0 0 0 hln 100 PCAD=PCB
a 0 u 13 0 0 0 hln 100 PADS=PCB
a 0 u 13 0 0 0 hln 100 ORCAD=PCB
a 0 u 13 0 0 0 hln 100 EDIF=PCB
a 0 u 13 0 0 0 hln 100 CADSTAR=PCB
a 0 u 13 0 0 0 hln 100 PSPICE=PSPICE
a 0 u 13 0 0 0 hln 100 XILINX=XILINX
@setup
unconnectedPins 0
connectViaLabel 0
connectViaLocalLabels 0
NoStim4ExtIFPortsWarnings 1
AutoGenStim4ExtIFPorts 1
@index
pageloc 1 0 3450 
@status
c 100:11:06:17:14:43;976140883
*page 1 0 970 720 iA
@ports
@parts
@conn
@junction
@attributes
a 0 s 0:13 0 0 0 hln 100 PAGETITLE=
a 0 s 0:13 0 0 0 hln 100 PAGENO=1
a 0 s 0:13 0 0 0 hln 100 PAGESIZE=A
a 0 s 0:13 0 0 0 hln 100 PAGECOUNT=1
@graphics
c 2 c 0 150 520 20
c 3 c 0 150 400 20
v 5 v 0 170 400
240 400
;
v 6 v 0 170 520
240 520
;
r 7 r 0 600 300 690 420
r 9 r 0 600 430 690 550
r 11 r 0 600 560 690 680
v 13 v 0 710 180
850 180
850 590
690 590
;
t 14 t 5 560 45 710 160 0 18 d_info:,,,,,,,,,,,,,25, 
Combination
Logic
r 15 r 0 550 30 710 270
v 16 v 0 710 240
810 240
810 330
690 330
;
v 17 v 0 710 210
830 210
830 460
690 460
;
v 18 v 0 600 330
390 330
;
t 19 t 5 600 314 640 350 0 2 d_info:,,,,,,,,,,,,,20, 
Q3
t 20 t 5 600 364 640 400 0 3 d_info:,,,,,,,,,,,,,20, 
Q3'
t 21 t 5 600 444 640 480 0 2 d_info:,,,,,,,,,,,,,20, 
Q2
t 22 t 5 600 494 640 530 0 3 d_info:,,,,,,,,,,,,,20, 
Q2'
t 23 t 5 600 574 640 610 0 2 d_info:,,,,,,,,,,,,,20, 
Q1
t 24 t 5 600 624 640 660 0 3 d_info:,,,,,,,,,,,,,20, 
Q1'
v 25 v 0 600 380
390 380
;
v 26 v 0 600 460
390 460
;
v 27 v 0 600 510
390 510
;
v 28 v 0 600 590
390 590
;
v 29 v 0 600 640
390 640
;
v 30 v 0 240 300
390 300
390 660
240 660
240 300
;
v 31 v 0 520 330
520 260
550 260
;
v 32 v 0 500 380
500 340
;
v 33 v 0 500 320
500 250
550 250
;
v 34 v 0 480 460
480 390
;
v 35 v 0 480 370
480 340
;
v 36 v 0 480 320
480 240
550 240
;
a 37 a 0 500 320 490 330 500 340 
a 38 a 0 480 320 470 330 480 340 
a 39 a 0 480 370 470 380 480 390 
a 40 a 0 460 450 450 460 460 470 
a 41 a 0 460 370 450 380 460 390 
a 42 a 0 460 320 450 330 460 340 
a 43 a 0 440 500 430 510 440 520 
a 44 a 0 440 450 430 460 440 470 
a 45 a 0 440 370 430 380 440 390 
a 46 a 0 440 320 430 330 440 340 
v 47 v 0 460 510
460 470
;
v 48 v 0 440 500
440 470
;
v 49 v 0 440 450
440 390
;
v 50 v 0 440 370
440 340
;
v 51 v 0 460 450
460 390
;
v 52 v 0 460 370
460 340
;
v 53 v 0 460 320
460 230
550 230
;
v 54 v 0 440 320
440 220
550 220
;
v 55 v 0 440 520
440 590
;
a 56 a 0 420 580 410 590 420 600 
a 57 a 0 420 500 410 510 420 520 
a 58 a 0 420 450 410 460 420 470 
a 59 a 0 420 370 410 380 420 390 
a 60 a 0 420 320 410 330 420 340 
v 61 v 0 420 640
420 600
;
v 62 v 0 420 580
420 520
;
v 63 v 0 420 500
420 470
;
v 64 v 0 420 450
420 390
;
v 65 v 0 420 370
420 340
;
v 66 v 0 420 320
420 210
550 210
;
v 67 v 0 550 80
420 80
;
t 68 t 5 360 44 420 110 0 11 d_info:,,,,,,,,,,,,,20, 
Input
   X
t 71 t 5 90 45 290 80 0 14 d_info:,,,,,,,,,,,,,25, 
Moore Counter:
v 72 v 0 690 380
670 390
690 400
;
v 73 v 0 690 510
670 520
690 530
;
v 74 v 0 690 640
670 650
690 660
;
v 75 v 0 690 390
730 390
730 450
;
v 76 v 0 730 470
730 580
;
v 77 v 0 730 600
730 650
690 650
;
a 78 a 0 730 450 720 460 730 470 
a 79 a 0 730 580 720 590 730 600 
v 80 v 0 730 630
780 630
;
t 81 t 5 780 614 840 650 0 5 d_info:,,,,,,,,,,,,,20, 
Clock
v 82 v 0 690 520
730 520
;
t 69 t 5 250 374 370 410 0 11 d_info:,,,,,,,,,,,,,20, 
N/S = (Q3')
t 70 t 5 250 504 370 540 0 10 d_info:,,,,,,,,,,,,,20, 
W/E = (Q3)
t 83 t 5 260 425 370 490 0 13 d_info:,,,,,,,,,,,,,25, 
Output
Logic
t 85 t 5 630 344 660 370 0 3 d_info:,,,,,,,,,,,,,15, 
(A)
t 86 t 5 630 474 660 500 0 3 d_info:,,,,,,,,,,,,,15, 
(B)
t 87 t 5 630 604 660 630 0 3 d_info:,,,,,,,,,,,,,15, 
(C)
t 8 t 5 660 314 690 350 0 2 d_info:,,,,,,,,,,,,,20, 
JK
t 10 t 5 660 444 690 480 0 2 d_info:,,,,,,,,,,,,,20, 
JK
t 12 t 5 660 574 690 610 0 2 d_info:,,,,,,,,,,,,,20, 
JK
t 84 t 5 120 74 250 100 0 19 d_info:,,,,,,,,,,,,,15, 
(with JK flip-flop)